On a Friday in 2022, Michal Privoznik wrote:
The PCIe 5.0 and PCIe 6.0 standards define new link speeds: 32GT/s and 64GT/s, respectively. Update our internal enum to include these new speeds. Otherwise we format incorrect XML: <pci-express> <link validity='cap' port='0' speed='(null)' width='16'/> <link validity='sta' speed='16' width='16'/> </pci-express> Like all "good" specifications, these are also locked behind a login portal. But we can look at pciutils' source code: [1] and [2]. 1: https://git.kernel.org/pub/scm/utils/pciutils/pciutils.git/commit/ls-caps.c?id=caca31a0eea41c7b051705704c1158fddc02fbd2 2: https://git.kernel.org/pub/scm/utils/pciutils/pciutils.git/commit/ls-caps.c?id=5bdf63b6b1bc35b59c4b3f47f7ca83ca1868155b Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=2105231 Signed-off-by: Michal Privoznik <mprivozn@xxxxxxxxxx> --- src/util/virpci.c | 2 +- src/util/virpci.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Ján Tomko <jtomko@xxxxxxxxxx> Jano
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