On Sat, Nov 20, 2021 at 1:17 PM Yifei Jiang <jiangyifei@xxxxxxxxxx> wrote:
>
> 'host' type cpu is set isa to RV32 or RV64 simply, more isa info
> will obtain from KVM in kvm_arch_init_vcpu()
>
> Signed-off-by: Yifei Jiang <jiangyifei@xxxxxxxxxx>
> Signed-off-by: Mingwang Li <limingwang@xxxxxxxxxx>
> Reviewed-by: Alistair Francis <alistair.francis@xxxxxxx>
Looks good to me.
Reviewed-by: Anup Patel <anup.patel@xxxxxxx>
Regards,
Anup
> ---
> target/riscv/cpu.c | 15 +++++++++++++++
> target/riscv/cpu.h | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a464845c99..6512182c62 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -247,6 +247,18 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> }
> #endif
>
> +#if defined(CONFIG_KVM)
> +static void riscv_host_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> +#if defined(TARGET_RISCV32)
> + set_misa(env, MXL_RV32, 0);
> +#elif defined(TARGET_RISCV64)
> + set_misa(env, MXL_RV64, 0);
> +#endif
> +}
> +#endif
> +
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> {
> ObjectClass *oc;
> @@ -844,6 +856,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .class_init = riscv_cpu_class_init,
> },
> DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> +#if defined(CONFIG_KVM)
> + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
> +#endif
> #if defined(TARGET_RISCV32)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 2807eb1bcb..e7dba35acb 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -45,6 +45,7 @@
> #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
> #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
> +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
>
> #if defined(TARGET_RISCV32)
> # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
> --
> 2.19.1
>
>
> --
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> kvm-riscv@xxxxxxxxxxxxxxxxxxx
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