Patchew URL: https://patchew.org/QEMU/20210107222253.20382-1-f4bug@xxxxxxxxx/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210107222253.20382-1-f4bug@xxxxxxxxx Subject: [PULL 00/66] MIPS patches for 2021-01-07 === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 >From https://github.com/patchew-project/qemu * [new tag] patchew/20210107222253.20382-1-f4bug@xxxxxxxxx -> patchew/20210107222253.20382-1-f4bug@xxxxxxxxx Switched to a new branch 'test' dd377f9 docs/system: Remove deprecated 'fulong2e' machine alias 46b7515 target/mips: Convert Rel6 LL/SC opcodes to decodetree 30b29c5 target/mips: Convert Rel6 LLD/SCD opcodes to decodetree a3a47cc target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree d31fb71 target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree 4ef5b18 target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree 218216b target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree ce5072b target/mips: Convert Rel6 COP1X opcode to decodetree 1ac8160 target/mips: Convert Rel6 Special2 opcode to decodetree 02dbc3d target/mips: Remove now unreachable LSA/DLSA opcodes code 36d8c0e target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes b862386 target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes 992d01e target/mips: Extract LSA/DLSA translation generators aa36e31 target/mips: Use decode_ase_msa() generated from decodetree 779aa4f target/mips: Introduce decode tree bindings for MSA ASE e0b0e2b target/mips: Pass TCGCond argument to MSA gen_check_zero_element() e844e9c target/mips: Extract MSA translation routines 574002a target/mips: Declare gen_msa/_branch() in 'translate.h' e2ebaf4 target/mips: Extract MSA helper definitions 5c3ca1b target/mips: Extract MSA helpers from op_helper.c ff8dd85 target/mips: Move msa_reset() to msa_helper.c 187fc34 target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() f6e81a3 target/mips: Remove CPUMIPSState* argument from gen_msa*() methods 5717a13 target/mips: Extract msa_translate_init() from mips_tcg_init() b41e6f5 target/mips: Alias MSA vector registers on FPU scalar registers 5dca6da target/mips: Remove now unused ASE_MSA definition 279cca1 target/mips: Simplify MSA TCG logic 9be6e1d target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA dd2ba3a target/mips: Simplify msa_reset() a6f9803 target/mips: Introduce ase_msa_available() helper 154d914 target/mips/translate: Expose check_mips_64() to 32-bit mode 4ad62c0 target/mips/translate: Extract decode_opc_legacy() from decode_opc() ae2962d target/mips: Only build TCG code when CONFIG_TCG is set bf286b1 target/mips: Extract FPU specific definitions to translate.h d664570 target/mips: Declare generic FPU functions in 'translate.h' 7d45714 target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction 4a7f56f target/mips: Replace gen_exception_err(err=0) by gen_exception_end() 734af7c target/mips/translate: Add declarations for generic code 7dbaf2f target/mips/translate: Extract DisasContext structure e31d0fb target/mips: Rename translate_init.c as cpu-defs.c 01c87b9 target/mips: Move mmu_init() functions to tlb_helper.c bf9cbc3 target/mips: Fix code style for checkpatch.pl 597531a target/mips: Rename helper.c as tlb_helper.c d1c9757 target/mips: Move common helpers from helper.c to cpu.c 514bb31 target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs 0a0492f target/mips: Add !CONFIG_USER_ONLY comment after #endif 304a3f9 target/mips: Extract FPU helpers to 'fpu_helper.h' 8967642 target/mips: Inline cpu_state_reset() in mips_cpu_reset() fd2629f target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 68cef79 target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 61f4a6e target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 befb8ce target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 cf55264 target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 6800c8b target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 64d02b6 target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 1917e3e target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 3440107 target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 b88e862 target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 d34977c hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() 43146ba target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() 9be76d4 target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 58b6d94 target/mips/mips-defs: Reorder CPU_MIPS5 definition b57df71 target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment aa10029 target/mips/addr: Add translation helpers for KSEG1 e8a10b7 target/mips: Replace CP0_Config0 magic values by proper definitions e4db93c target/mips: Add CP0 Config0 register definitions for MIPS3 ISA === OUTPUT BEGIN === 1/66 Checking commit e4db93c23d92 (target/mips: Add CP0 Config0 register definitions for MIPS3 ISA) 2/66 Checking commit e8a10b733538 (target/mips: Replace CP0_Config0 magic values by proper definitions) 3/66 Checking commit aa1002921075 (target/mips/addr: Add translation helpers for KSEG1) 4/66 Checking commit b57df718455b (target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment) 5/66 Checking commit 58b6d941ecc4 (target/mips/mips-defs: Reorder CPU_MIPS5 definition) 6/66 Checking commit 9be76d48e0fe (target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1) 7/66 Checking commit 43146bacae19 (target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()) 8/66 Checking commit d34977c07407 (hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()) 9/66 Checking commit b88e8622d21f (target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1) 10/66 Checking commit 3440107bbb6f (target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2) 11/66 Checking commit 1917e3ef23d8 (target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3) 12/66 Checking commit 64d02b692008 (target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5) 13/66 Checking commit 6800c8b5c12e (target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6) 14/66 Checking commit cf552649ce52 (target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1) 15/66 Checking commit befb8ceccf7f (target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2) 16/66 Checking commit 61f4a6e201e4 (target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3) 17/66 Checking commit 68cef795e767 (target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5) 18/66 Checking commit fd2629f0f0d4 (target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6) 19/66 Checking commit 89676429d275 (target/mips: Inline cpu_state_reset() in mips_cpu_reset()) 20/66 Checking commit 304a3f9d18a1 (target/mips: Extract FPU helpers to 'fpu_helper.h') WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #39: new file mode 100644 total: 0 errors, 1 warnings, 193 lines checked Patch 20/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 21/66 Checking commit 0a0492fcd800 (target/mips: Add !CONFIG_USER_ONLY comment after #endif) 22/66 Checking commit 514bb3169df2 (target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs) 23/66 Checking commit d1c975707e12 (target/mips: Move common helpers from helper.c to cpu.c) ERROR: space prohibited after that '&' (ctx:WxW) #40: FILE: target/mips/cpu.c:53: + cu = (v >> CP0St_CU0) & 0xf; ^ ERROR: space prohibited after that '&' (ctx:WxW) #41: FILE: target/mips/cpu.c:54: + mx = (v >> CP0St_MX) & 0x1; ^ ERROR: space prohibited after that '&' (ctx:WxW) #42: FILE: target/mips/cpu.c:55: + ksu = (v >> CP0St_KSU) & 0x3; ^ ERROR: space prohibited after that '&' (ctx:WxW) #69: FILE: target/mips/cpu.c:82: + uint32_t ksux = (1 << CP0St_KX) & val; ^ ERROR: space prohibited after that '&' (ctx:WxW) #77: FILE: target/mips/cpu.c:90: + mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); ^ ERROR: space prohibited after that '&' (ctx:WxW) #104: FILE: target/mips/cpu.c:117: + mask &= ~((1 << CP0Ca_WP) & val); ^ ERROR: space prohibited after that '&' (ctx:WxW) #109: FILE: target/mips/cpu.c:122: + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { ^ ERROR: space prohibited after that '&' (ctx:WxW) #119: FILE: target/mips/cpu.c:132: + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { ^ total: 8 errors, 0 warnings, 433 lines checked Patch 23/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 24/66 Checking commit 597531ae621e (target/mips: Rename helper.c as tlb_helper.c) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #33: rename from target/mips/helper.c total: 0 errors, 1 warnings, 17 lines checked Patch 24/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 25/66 Checking commit bf9cbc309ca7 (target/mips: Fix code style for checkpatch.pl) 26/66 Checking commit 01c87b9da531 (target/mips: Move mmu_init() functions to tlb_helper.c) 27/66 Checking commit e31d0fb8b891 (target/mips: Rename translate_init.c as cpu-defs.c) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #17: rename from target/mips/translate_init.c.inc total: 0 errors, 1 warnings, 8 lines checked Patch 27/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 28/66 Checking commit 7dbaf2f8475b (target/mips/translate: Extract DisasContext structure) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #73: new file mode 100644 total: 0 errors, 1 warnings, 100 lines checked Patch 28/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 29/66 Checking commit 734af7c7cd5f (target/mips/translate: Add declarations for generic code) 30/66 Checking commit 4a7f56f756f1 (target/mips: Replace gen_exception_err(err=0) by gen_exception_end()) 31/66 Checking commit 7d45714935f0 (target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction) 32/66 Checking commit d664570b4d0e (target/mips: Declare generic FPU functions in 'translate.h') 33/66 Checking commit bf286b108260 (target/mips: Extract FPU specific definitions to translate.h) 34/66 Checking commit ae2962d6ae59 (target/mips: Only build TCG code when CONFIG_TCG is set) 35/66 Checking commit 4ad62c011a12 (target/mips/translate: Extract decode_opc_legacy() from decode_opc()) 36/66 Checking commit 154d914967f5 (target/mips/translate: Expose check_mips_64() to 32-bit mode) 37/66 Checking commit a6f9803fd299 (target/mips: Introduce ase_msa_available() helper) 38/66 Checking commit dd2ba3abe7b4 (target/mips: Simplify msa_reset()) 39/66 Checking commit 9be6e1d7f765 (target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA) 40/66 Checking commit 279cca136d3f (target/mips: Simplify MSA TCG logic) 41/66 Checking commit 5dca6da28810 (target/mips: Remove now unused ASE_MSA definition) 42/66 Checking commit b41e6f53d419 (target/mips: Alias MSA vector registers on FPU scalar registers) 43/66 Checking commit 5717a131e32b (target/mips: Extract msa_translate_init() from mips_tcg_init()) 44/66 Checking commit f6e81a3cc0c8 (target/mips: Remove CPUMIPSState* argument from gen_msa*() methods) 45/66 Checking commit 187fc3480672 (target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()) 46/66 Checking commit ff8dd8556127 (target/mips: Move msa_reset() to msa_helper.c) 47/66 Checking commit 5c3ca1b4d69d (target/mips: Extract MSA helpers from op_helper.c) 48/66 Checking commit e2ebaf4ae29e (target/mips: Extract MSA helper definitions) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #461: new file mode 100644 total: 0 errors, 1 warnings, 883 lines checked Patch 48/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 49/66 Checking commit 574002aa479c (target/mips: Declare gen_msa/_branch() in 'translate.h') 50/66 Checking commit e844e9c880a9 (target/mips: Extract MSA translation routines) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #31: new file mode 100644 total: 0 errors, 1 warnings, 4551 lines checked Patch 50/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 51/66 Checking commit e0b0e2b8f499 (target/mips: Pass TCGCond argument to MSA gen_check_zero_element()) 52/66 Checking commit 779aa4f7226b (target/mips: Introduce decode tree bindings for MSA ASE) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #35: new file mode 100644 total: 0 errors, 1 warnings, 103 lines checked Patch 52/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 53/66 Checking commit aa36e31acb54 (target/mips: Use decode_ase_msa() generated from decodetree) 54/66 Checking commit 992d01ed4aaa (target/mips: Extract LSA/DLSA translation generators) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #119: new file mode 100644 total: 0 errors, 1 warnings, 145 lines checked Patch 54/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 55/66 Checking commit b862386020fc (target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #48: new file mode 100644 total: 0 errors, 1 warnings, 65 lines checked Patch 55/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 56/66 Checking commit 36d8c0ede396 (target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #36: new file mode 100644 WARNING: line over 80 characters #133: FILE: target/mips/translate.c:29031: + if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) { total: 0 errors, 2 warnings, 102 lines checked Patch 56/66 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 57/66 Checking commit 02dbc3d3d79b (target/mips: Remove now unreachable LSA/DLSA opcodes code) 58/66 Checking commit 1ac816021bc6 (target/mips: Convert Rel6 Special2 opcode to decodetree) 59/66 Checking commit ce5072b957f9 (target/mips: Convert Rel6 COP1X opcode to decodetree) 60/66 Checking commit 218216b9e8dd (target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree) 61/66 Checking commit 4ef5b183d3bb (target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree) 62/66 Checking commit d31fb7133964 (target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree) 63/66 Checking commit a3a47cc9c1fc (target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree) 64/66 Checking commit 30b29c544e10 (target/mips: Convert Rel6 LLD/SCD opcodes to decodetree) 65/66 Checking commit 46b75150a917 (target/mips: Convert Rel6 LL/SC opcodes to decodetree) 66/66 Checking commit dd377f9d6f40 (docs/system: Remove deprecated 'fulong2e' machine alias) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20210107222253.20382-1-f4bug@xxxxxxxxx/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. 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