Re: [PATCH] Expose resource control capabilites on cache bank

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On Thursday, 6 April 2017 at 6:10 PM, Daniel P. Berrange wrote:

On Thu, Apr 06, 2017 at 12:05:54PM +0200, Martin Kletzander wrote:
On Thu, Apr 06, 2017 at 10:51:44AM +0100, Daniel P. Berrange wrote:
On Thu, Apr 06, 2017 at 11:49:14AM +0200, Martin Kletzander wrote:
On Thu, Apr 06, 2017 at 04:20:06PM +0800, Eli Qiao wrote:
This patch is based on Martin's cache branch.

This patch amends the cache bank capability as follow:

<bank id='0' level='3' type='unified' size='15360' unit='KiB' cpus='0-5'/>
<control min='768' unit='KiB' type='unified' nclos='4'/>
<bank id='1' level='3' type='unified' size='15360' unit='KiB' cpus='6-11'/>
<control min='768' unit='KiB' type='unified' nclos='4'/>

Either the XML is malformed, or the indentation is wrong. The indentation
suggests you want nested XML elements, but the parent element is an empty
tag, so you've actually got a flat namespace here.


Were we exposing the number of CLoS IDs before? Was there a discussion
about it? Do we want to expose them? Probably yes, I'm just wondering.

What are CLoS IDs and what are they used for ?

Effectively an ID for the allocation. The hardware has a limited number
of them, in this case 4. I can't remember whether that number is
per-bank, but it would not make much sense otherwise.

So, if guests are requesting a private cache allocation, and cos id == 4,
then we can only run 4 guests ?

I think yes, but it’s per bank resource (the bank here is equal to cache id), if you have 2 banks , you can create 8 guests (each has 1 bank allocation)

As far as I know, the number of clos id is 16 on most of Intel xeon CPUs

Regards,
Daniel
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