On Thu, Mar 09, 2017 at 03:12:09PM -0300, Eduardo Habkost wrote: > I plan to merge this bug fix into 2.9. I'm queueing this on my x86-next branch. > > Changes v2 -> v3: > * Rebase to latest master > * Don't touch max_x86_cpu_initfn() to reduce risk post > hard freeze > > Changes v1 -> v2: > * Coding style fixes > * Make series simpler: > * Don't use trick: char vendor[static (CPUID_VENDOR_SZ + 1)] > because it confuses checkpatch.pl > * Removed patch "Add explicit array size to x86_cpu_vendor_words2str()" > * Rebased on top of my x86-next branch: > https://github.com/ehabkost/qemu x86-next > > Git branch for testing: > https://github.com/ehabkost/qemu-hacks work/x86-rtm-blacklist > > Diff from v1: > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index cd94726e43..647435a1d9 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -1431,7 +1431,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > void cpu_clear_apic_feature(CPUX86State *env); > void host_cpuid(uint32_t function, uint32_t count, > uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); > -void host_vendor_fms(char vendor[static (CPUID_VENDOR_SZ + 1)], int *family, int *model, int *stepping); > +void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); > > /* helper.c */ > int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 25c6c5e115..eab1ad7935 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -682,7 +682,7 @@ void host_cpuid(uint32_t function, uint32_t count, > *edx = vec[3]; > } > > -void host_vendor_fms(char vendor[static (CPUID_VENDOR_SZ + 1)], int *family, int *model, int *stepping) > +void host_vendor_fms(char *vendor, int *family, int *model, int *stepping) > { > uint32_t eax, ebx, ecx, edx; > > @@ -1570,7 +1570,8 @@ static void host_x86_cpu_class_init(ObjectClass *oc, void *data) > xcc->kvm_required = true; > xcc->ordering = 9; > > - host_vendor_fms(host_cpudef.vendor, &host_cpudef.family, &host_cpudef.model, &host_cpudef.stepping); > + host_vendor_fms(host_cpudef.vendor, &host_cpudef.family, > + &host_cpudef.model, &host_cpudef.stepping); > > cpu_x86_fill_model_id(host_cpudef.model_id); > > --- > > A recent glibc commit[1] added a blacklist to ensure it won't use > TSX on hosts that are known to have a broken TSX implementation. > > Our existing Haswell CPU model has a blacklisted > family/model/stepping combination, so it has to be updated to > make sure guests will really use TSX. This is done by patch 5/5. > > However, to do this safely we need to ensure the host CPU is not > a blacklisted one, so we won't mislead guests by exposing > known-to-be-good FMS values on a known-to-be-broken host. This is > done by patch 3/5. > > [1] https://sourceware.org/git/?p=glibc.git;a=commit;h=2702856bf45c82cf8e69f2064f5aa15c0ceb6359 > > --- > Cc: dgilbert@xxxxxxxxxx > Cc: fweimer@xxxxxxxxxx > Cc: carlos@xxxxxxxxxx > Cc: triegel@xxxxxxxxxx > Cc: berrange@xxxxxxxxxx > Cc: jdenemar@xxxxxxxxxx > Cc: pbonzini@xxxxxxxxxx > > Eduardo Habkost (3): > i386: host_vendor_fms() helper function > i386/kvm: Blacklist TSX on known broken hosts > i386: Change stepping of Haswell to non-blacklisted value > > include/hw/i386/pc.h | 5 +++++ > target/i386/cpu.h | 1 + > target/i386/cpu.c | 21 ++++++++++++++++++++- > target/i386/kvm.c | 17 +++++++++++++++++ > 4 files changed, 43 insertions(+), 1 deletion(-) > > -- > 2.11.0.259.g40922b1 > > -- Eduardo -- libvir-list mailing list libvir-list@xxxxxxxxxx https://www.redhat.com/mailman/listinfo/libvir-list
