[PATCH 6/7] perf: add cache_l1dpm perf event support

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This patch adds support and documentation for
a generalized hardware cache event named cache_l1dpm
perf event for measuring prefetch misses on level 1
data cache

Signed-off-by: Nitesh Konkar <nitkon12@xxxxxxxxxxxxxxxxxx>
---
 docs/formatdomain.html.in                   |  7 +++++++
 docs/news.xml                               |  3 ++-
 docs/schemas/domaincommon.rng               |  1 +
 include/libvirt/libvirt-domain.h            | 11 +++++++++++
 src/libvirt-domain.c                        |  3 +++
 src/qemu/qemu_driver.c                      |  1 +
 src/util/virperf.c                          |  7 ++++++-
 src/util/virperf.h                          |  1 +
 tests/genericxml2xmlindata/generic-perf.xml |  1 +
 tools/virsh.pod                             |  3 +++
 10 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/docs/formatdomain.html.in b/docs/formatdomain.html.in
index 245120d..179efe3 100644
--- a/docs/formatdomain.html.in
+++ b/docs/formatdomain.html.in
@@ -1942,6 +1942,7 @@
   &lt;event name='cache_l1dwa' enabled='no'/&gt;
   &lt;event name='cache_l1dwm' enabled='no'/&gt;
   &lt;event name='cache_l1dpa' enabled='no'/&gt;
+  &lt;event name='cache_l1dpm' enabled='no'/&gt;
 &lt;/perf&gt;
 ...
 </pre>
@@ -2050,6 +2051,12 @@
           cache by applications running on the platform</td>
       <td><code>perf.cache_l1dpa</code></td>
     </tr>
+    <tr>
+      <td><code>cache_l1dpm</code></td>
+      <td>the count of total prefetch misses for level 1 data
+          cache by applications running on the platform</td>
+      <td><code>perf.cache_l1dpm</code></td>
+    </tr>
   </table>
 
     <h3><a name="elementsDevices">Devices</a></h3>
diff --git a/docs/news.xml b/docs/news.xml
index 1f362e2..954c2af 100644
--- a/docs/news.xml
+++ b/docs/news.xml
@@ -108,7 +108,8 @@
           executed, branch misses, bus cycles, stalled frontend
           cpu cycles, stalled backend cpu cycles, ref cpu cycles,
           cache l1dra, cache l1drm, cache l1dwa, cache l1dwm,
-          cache l1dpa by applications running on the platform.
+          cache l1dpa and cache l1dpm by applications running on
+          the platform.
         </description>
       </change>
       <change>
diff --git a/docs/schemas/domaincommon.rng b/docs/schemas/domaincommon.rng
index 83a205a..05d3579 100644
--- a/docs/schemas/domaincommon.rng
+++ b/docs/schemas/domaincommon.rng
@@ -438,6 +438,7 @@
               <value>cache_l1dwa</value>
               <value>cache_l1dwm</value>
               <value>cache_l1dpa</value>
+              <value>cache_l1dpm</value>
             </choice>
           </attribute>
           <attribute name="enabled">
diff --git a/include/libvirt/libvirt-domain.h b/include/libvirt/libvirt-domain.h
index 9db4969..6c84c98 100644
--- a/include/libvirt/libvirt-domain.h
+++ b/include/libvirt/libvirt-domain.h
@@ -2243,6 +2243,17 @@ void virDomainStatsRecordListFree(virDomainStatsRecordPtr *stats);
  */
 # define VIR_PERF_PARAM_CACHE_L1DPA "cache_l1dpa"
 
+/*
+ * VIR_PERF_PARAM_CACHE_L1DPM:
+ *
+ *Macro for typed parameter name that represents cache_l1dpm
+ *perf event which can be used to measure the count of total
+ *prefetch misses for level 1 data cache by applications
+ *running on the platform. It corresponds to the
+ *"perf.cache_l1dpm" field in the *Stats APIs.
+ */
+# define VIR_PERF_PARAM_CACHE_L1DPM "cache_l1dpm"
+
 int virDomainGetPerfEvents(virDomainPtr dom,
                            virTypedParameterPtr *params,
                            int *nparams,
diff --git a/src/libvirt-domain.c b/src/libvirt-domain.c
index 089d3f5..1f34175 100644
--- a/src/libvirt-domain.c
+++ b/src/libvirt-domain.c
@@ -11265,6 +11265,9 @@ virConnectGetDomainCapabilities(virConnectPtr conn,
  *     "perf.cache_l1dpa" - The count of total prefetch accesses for level 1
  *                          data cache as unsigned long long. It is produced by
  *                          cache_l1dpa perf event.
+ *     "perf.cache_l1dpm" - The count of total prefetch misses for level 1
+ *                          data cache as unsigned long long. It is produced by
+ *                          cache_l1dpm perf event.
  *
  * Note that entire stats groups or individual stat fields may be missing from
  * the output in case they are not supported by the given hypervisor, are not
diff --git a/src/qemu/qemu_driver.c b/src/qemu/qemu_driver.c
index 8acb706..356bc38 100644
--- a/src/qemu/qemu_driver.c
+++ b/src/qemu/qemu_driver.c
@@ -9882,6 +9882,7 @@ qemuDomainSetPerfEvents(virDomainPtr dom,
                                VIR_PERF_PARAM_CACHE_L1DWA, VIR_TYPED_PARAM_BOOLEAN,
                                VIR_PERF_PARAM_CACHE_L1DWM, VIR_TYPED_PARAM_BOOLEAN,
                                VIR_PERF_PARAM_CACHE_L1DPA, VIR_TYPED_PARAM_BOOLEAN,
+                               VIR_PERF_PARAM_CACHE_L1DPM, VIR_TYPED_PARAM_BOOLEAN,
                                NULL) < 0)
         return -1;
 
diff --git a/src/util/virperf.c b/src/util/virperf.c
index df2a91a..788b817 100644
--- a/src/util/virperf.c
+++ b/src/util/virperf.c
@@ -45,7 +45,7 @@ VIR_ENUM_IMPL(virPerfEvent, VIR_PERF_EVENT_LAST,
               "bus_cycles", "stalled_cycles_frontend",
               "stalled_cycles_backend", "ref_cpu_cycles",
               "cache_l1dra", "cache_l1drm", "cache_l1dwa",
-              "cache_l1dwm", "cache_l1dpa");
+              "cache_l1dwm", "cache_l1dpa", "cache_l1dpm");
 
 struct virPerfEvent {
     int type;
@@ -139,6 +139,11 @@ static struct virPerfEventAttr attrs[] = {
      .attrConfig = (PERF_COUNT_HW_CACHE_L1D) |
                    (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
                    (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)},
+    {.type = VIR_PERF_EVENT_CACHE_L1DPM,
+     .attrType = PERF_TYPE_HW_CACHE,
+     .attrConfig = (PERF_COUNT_HW_CACHE_L1D) |
+                   (PERF_COUNT_HW_CACHE_OP_PREFETCH << 8) |
+                   (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)},
 };
 typedef struct virPerfEventAttr *virPerfEventAttrPtr;
 
diff --git a/src/util/virperf.h b/src/util/virperf.h
index 78c8557..1ec5c3a 100644
--- a/src/util/virperf.h
+++ b/src/util/virperf.h
@@ -52,6 +52,7 @@ typedef enum {
     VIR_PERF_EVENT_CACHE_L1DWA, /* Count of write accesses for level 1 data cache */
     VIR_PERF_EVENT_CACHE_L1DWM, /* Count of write misses for level 1 data cache */
     VIR_PERF_EVENT_CACHE_L1DPA, /* Count of prefetch accesses for level 1 data cache */
+    VIR_PERF_EVENT_CACHE_L1DPM, /* Count of prefetch misses for level 1 data cache */
 
     VIR_PERF_EVENT_LAST
 } virPerfEventType;
diff --git a/tests/genericxml2xmlindata/generic-perf.xml b/tests/genericxml2xmlindata/generic-perf.xml
index a575f89..875d092 100644
--- a/tests/genericxml2xmlindata/generic-perf.xml
+++ b/tests/genericxml2xmlindata/generic-perf.xml
@@ -31,6 +31,7 @@
     <event name='cache_l1dwa' enabled='yes'/>
     <event name='cache_l1dwm' enabled='yes'/>
     <event name='cache_l1dpa' enabled='yes'/>
+    <event name='cache_l1dpm' enabled='yes'/>
   </perf>
   <devices>
   </devices>
diff --git a/tools/virsh.pod b/tools/virsh.pod
index c599aa5..467a7d6 100644
--- a/tools/virsh.pod
+++ b/tools/virsh.pod
@@ -951,6 +951,7 @@ I<--perf> returns the statistics of all enabled perf events:
 "perf.cache_l1dwa" - the count of write accesses for level 1 data cache,
 "perf.cache_l1dwm" - the count of write misses for level 1 data cache,
 "perf.cache_l1dpa" - the count of prefetch accesses for level 1 data cache
+"perf.cache_l1dpm" - the count of prefetch misses for level 1 data cache
 
 See the B<perf> command for more details about each event.
 
@@ -2325,6 +2326,8 @@ B<Valid perf event names>
                 data cache by applications running on the platform.
   cache_l1dpa - Provides the count of total prefetch accesses for
                 level 1 data cache by applications running on the platform.
+  cache_l1dpm - Provides the count of total prefetch misses for level 1
+                data cache by applications running on the platform.
 
 B<Note>: The statistics can be retrieved using the B<domstats> command using
 the I<--perf> flag.
-- 
1.9.3

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