[PATCH 2/7] perf: add cache_l1drm perf event support

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



This patch adds support and documentation for
a generalized hardware cache event named cache_l1drm
perf event for measuring read misses on level 1
data cache

Signed-off-by: Nitesh Konkar <nitkon12@xxxxxxxxxxxxxxxxxx>
---
 docs/formatdomain.html.in                   |  7 +++++++
 docs/news.xml                               |  5 +++--
 docs/schemas/domaincommon.rng               |  1 +
 include/libvirt/libvirt-domain.h            | 11 +++++++++++
 src/libvirt-domain.c                        |  3 +++
 src/qemu/qemu_driver.c                      |  1 +
 src/util/virperf.c                          |  7 ++++++-
 src/util/virperf.h                          |  1 +
 tests/genericxml2xmlindata/generic-perf.xml |  1 +
 tools/virsh.pod                             |  5 ++++-
 10 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/docs/formatdomain.html.in b/docs/formatdomain.html.in
index 20ef976..9db6d38 100644
--- a/docs/formatdomain.html.in
+++ b/docs/formatdomain.html.in
@@ -1938,6 +1938,7 @@
   &lt;event name='stalled_cycles_backend' enabled='no'/&gt;
   &lt;event name='ref_cpu_cycles' enabled='no'/&gt;
   &lt;event name='cache_l1dra' enabled='no'/&gt;
+  &lt;event name='cache_l1drm' enabled='no'/&gt;
 &lt;/perf&gt;
 ...
 </pre>
@@ -2022,6 +2023,12 @@
           applications running on the platform</td>
       <td><code>perf.cache_l1dra</code></td>
     </tr>
+    <tr>
+      <td><code>cache_l1drm</code></td>
+      <td>the count of total read misses for level 1 data cache by
+          applications running on the platform</td>
+      <td><code>perf.cache_l1drm</code></td>
+    </tr>
   </table>
 
     <h3><a name="elementsDevices">Devices</a></h3>
diff --git a/docs/news.xml b/docs/news.xml
index b31d0a4..fe83ce4 100644
--- a/docs/news.xml
+++ b/docs/news.xml
@@ -106,8 +106,9 @@
         <description>
           Add support to get the count of branch instructions
           executed, branch misses, bus cycles, stalled frontend
-          cpu cycles, stalled backend cpu cycles, ref cpu cycles
-          and cache l1dra by applications running on the platform.
+          cpu cycles, stalled backend cpu cycles, ref cpu cycles,
+          cache l1dra and cache l1drm by applications running on
+          the platform.
         </description>
       </change>
       <change>
diff --git a/docs/schemas/domaincommon.rng b/docs/schemas/domaincommon.rng
index a65ad13..6a7c83c 100644
--- a/docs/schemas/domaincommon.rng
+++ b/docs/schemas/domaincommon.rng
@@ -434,6 +434,7 @@
               <value>stalled_cycles_backend</value>
               <value>ref_cpu_cycles</value>
               <value>cache_l1dra</value>
+              <value>cache_l1drm</value>
             </choice>
           </attribute>
           <attribute name="enabled">
diff --git a/include/libvirt/libvirt-domain.h b/include/libvirt/libvirt-domain.h
index e2ba6ce..abf0e14 100644
--- a/include/libvirt/libvirt-domain.h
+++ b/include/libvirt/libvirt-domain.h
@@ -2199,6 +2199,17 @@ void virDomainStatsRecordListFree(virDomainStatsRecordPtr *stats);
  */
 # define VIR_PERF_PARAM_CACHE_L1DRA "cache_l1dra"
 
+/**
+ * VIR_PERF_PARAM_CACHE_L1DRM:
+ *
+ * Macro for typed parameter name that represents cache_l1drm
+ * perf event which can be used to measure the count of total
+ * read misses for level 1 data cache by applications running
+ * on the platform. It corresponds to the "perf.cache_l1drm"
+ * field in the *Stats APIs.
+ */
+# define VIR_PERF_PARAM_CACHE_L1DRM "cache_l1drm"
+
 int virDomainGetPerfEvents(virDomainPtr dom,
                            virTypedParameterPtr *params,
                            int *nparams,
diff --git a/src/libvirt-domain.c b/src/libvirt-domain.c
index fa39069..7183905 100644
--- a/src/libvirt-domain.c
+++ b/src/libvirt-domain.c
@@ -11253,6 +11253,9 @@ virConnectGetDomainCapabilities(virConnectPtr conn,
  *     "perf.cache_l1dra" - The count of total read accesses for level 1 data
  *                          cache as unsigned long long. It is produced by
  *                          cache_l1dra perf event.
+ *     "perf.cache_l1drm" - The count of total read misses for level 1 data
+ *                          cache as unsigned long long. It is produced by
+ *                          cache_l1drm perf event.
  *
  * Note that entire stats groups or individual stat fields may be missing from
  * the output in case they are not supported by the given hypervisor, are not
diff --git a/src/qemu/qemu_driver.c b/src/qemu/qemu_driver.c
index 7e2ea96..da50f95 100644
--- a/src/qemu/qemu_driver.c
+++ b/src/qemu/qemu_driver.c
@@ -9878,6 +9878,7 @@ qemuDomainSetPerfEvents(virDomainPtr dom,
                                VIR_PERF_PARAM_STALLED_CYCLES_BACKEND, VIR_TYPED_PARAM_BOOLEAN,
                                VIR_PERF_PARAM_REF_CPU_CYCLES, VIR_TYPED_PARAM_BOOLEAN,
                                VIR_PERF_PARAM_CACHE_L1DRA, VIR_TYPED_PARAM_BOOLEAN,
+                               VIR_PERF_PARAM_CACHE_L1DRM, VIR_TYPED_PARAM_BOOLEAN,
                                NULL) < 0)
         return -1;
 
diff --git a/src/util/virperf.c b/src/util/virperf.c
index 11e64df..4b9fc9a 100644
--- a/src/util/virperf.c
+++ b/src/util/virperf.c
@@ -44,7 +44,7 @@ VIR_ENUM_IMPL(virPerfEvent, VIR_PERF_EVENT_LAST,
               "branch_instructions", "branch_misses",
               "bus_cycles", "stalled_cycles_frontend",
               "stalled_cycles_backend", "ref_cpu_cycles",
-              "cache_l1dra");
+              "cache_l1dra", "cache_l1drm");
 
 struct virPerfEvent {
     int type;
@@ -118,6 +118,11 @@ static struct virPerfEventAttr attrs[] = {
      .attrConfig = (PERF_COUNT_HW_CACHE_L1D) |
                    (PERF_COUNT_HW_CACHE_OP_READ << 8) |
                    (PERF_COUNT_HW_CACHE_RESULT_ACCESS << 16)},
+    {.type = VIR_PERF_EVENT_CACHE_L1DRM,
+     .attrType = PERF_TYPE_HW_CACHE,
+     .attrConfig = (PERF_COUNT_HW_CACHE_L1D) |
+                   (PERF_COUNT_HW_CACHE_OP_READ << 8) |
+                   (PERF_COUNT_HW_CACHE_RESULT_MISS << 16)},
 };
 typedef struct virPerfEventAttr *virPerfEventAttrPtr;
 
diff --git a/src/util/virperf.h b/src/util/virperf.h
index 36ceb3a..37058b0 100644
--- a/src/util/virperf.h
+++ b/src/util/virperf.h
@@ -48,6 +48,7 @@ typedef enum {
                                               processor pipeline */
     VIR_PERF_EVENT_REF_CPU_CYCLES,   /* Count of ref cpu cycles */
     VIR_PERF_EVENT_CACHE_L1DRA, /* Count of read accesses for level 1 data cache */
+    VIR_PERF_EVENT_CACHE_L1DRM, /* Count of read misses for level 1 data cache */
 
     VIR_PERF_EVENT_LAST
 } virPerfEventType;
diff --git a/tests/genericxml2xmlindata/generic-perf.xml b/tests/genericxml2xmlindata/generic-perf.xml
index 9b01aef..bb8a085 100644
--- a/tests/genericxml2xmlindata/generic-perf.xml
+++ b/tests/genericxml2xmlindata/generic-perf.xml
@@ -27,6 +27,7 @@
     <event name='stalled_cycles_backend' enabled='yes'/>
     <event name='ref_cpu_cycles' enabled='yes'/>
     <event name='cache_l1dra' enabled='yes'/>
+    <event name='cache_l1drm' enabled='yes'/>
   </perf>
   <devices>
   </devices>
diff --git a/tools/virsh.pod b/tools/virsh.pod
index 798c02e..c1bdbdd 100644
--- a/tools/virsh.pod
+++ b/tools/virsh.pod
@@ -946,7 +946,8 @@ I<--perf> returns the statistics of all enabled perf events:
 "perf.stalled_cycles_frontend" - the count of stalled frontend cpu cycles,
 "perf.stalled_cycles_backend" - the count of stalled backend cpu cycles,
 "perf.ref_cpu_cycles" - the count of ref cpu cycles,
-"perf.cache_l1dra" - the count of read accesses for level 1 data cache
+"perf.cache_l1dra" - the count of read accesses for level 1 data cache,
+"perf.cache_l1drm" - the count of read misses for level 1 data cache
 
 See the B<perf> command for more details about each event.
 
@@ -2313,6 +2314,8 @@ B<Valid perf event names>
                       applications running on the platform.
   cache_l1dra - Provides the count of total read accesses for level 1
                 data cache by applications running on the platform.
+  cache_l1drm - Provides the count of total read misses for level 1
+                data cache by applications running on the platform.
 
 B<Note>: The statistics can be retrieved using the B<domstats> command using
 the I<--perf> flag.
-- 
1.9.3

--
libvir-list mailing list
libvir-list@xxxxxxxxxx
https://www.redhat.com/mailman/listinfo/libvir-list



[Index of Archives]     [Virt Tools]     [Libvirt Users]     [Lib OS Info]     [Fedora Users]     [Fedora Desktop]     [Fedora SELinux]     [Big List of Linux Books]     [Yosemite News]     [KDE Users]     [Fedora Tools]
  Powered by Linux