On Thu, Feb 26, 2009 at 02:56:13PM +0000, Daniel P. Berrange wrote: > > +/* PM12 3.2.4 Power Management Control/Status (Offset = 4) */ > > +#define PCI_PM_CTRL 4 /* PM control and status register */ > > +#define PCI_PM_CTRL_STATE_MASK 0x3 /* Current power state (D0 to D3) */ > > +#define PCI_PM_CTRL_STATE_D0 0x0 /* D0 state */ > > +#define PCI_PM_CTRL_STATE_D3hot 0x3 /* D3 state */ > > +#define PCI_PM_CTRL_NO_SOFT_RESET 0x4 /* No reset for D3hot->D0 */ > > I've been told off-list, that this last constant should be 0x8 instead > of 0x4 After googling a bit I found 0x8 on a PCI-SIG ENGINEERING document from 2005, so apparently yes. Daniel -- Daniel Veillard | libxml Gnome XML XSLT toolkit http://xmlsoft.org/ daniel@xxxxxxxxxxxx | Rpmfind RPM search engine http://rpmfind.net/ http://veillard.com/ | virtualization library http://libvirt.org/ -- Libvir-list mailing list Libvir-list@xxxxxxxxxx https://www.redhat.com/mailman/listinfo/libvir-list