On Mon, 2008-02-04 at 11:39 +0000, Alan Cox wrote: > > speed in the, then, current serial circuitry. If you could get faster, > > and accurate electronics, which you *now* can, serial can manage faster > > rates, easier and more reliably. > > No. > > The reason is quite different. When you have a parallel cable all the > wires are never quite the same length, diameter or metal properties > (ditto tracks on a board). That means that the signals arrive at the ends > of each wire at different times. Your clock rate is thus limited by the > cable quality and length as well as these propogation delays. That is > what limits PATA to UDMA/133. Any faster and the bits just won't turn up > on time. > > If you have one or more serial links with their own clock the clock > arrives with the data on that link as it does for example with ethernet. > > Alan > Actually most modern serial systems don't send a clock at all. The clock rate is recovered from the data using (surprise) a clock recovery circuit driving a Phase Locked Loop frequency synthesizer. Silicon is cheaper than wire these days. PC board layouts are much more constrained these days, so the old adage about board differences has moved quite a ways up the frequency spectrum, and there are specific materials which address some aspects of the insulator loss as well. PC boards are now etched with ultrasonic jets in some cases, or for really finite control, with lasers to trim the results. CAD software has reduced the errors in layout, and improvements in simulation permit modeling the PC board interaction and signal delivery prior to creating the actual PC board. I have used PC layout up to 8Ghz successfully with correlation to a bit better than six sigma. It is all a matter of attention to detail, with the use of modern tools. The biggest repeatability issue these days are the sockets for the devices. Trying to lift an SHF or microwave signal from a trace to a device is tough. When the device is to be fix mounted, you can resort to relieving the PC board, and mounting the pin grid in line with the traces, yielding an mmic form of signal transition. But if the device has a thousand pins (think 64 bit DDR2 interface) then something called ball grid mounting becomes more or less mandatory, with lots of little grounds interspersed to provide isolation and impedance control. The signal then has to make a series of minute 90 degree transitions from trace to ball to pad to silicon, and each transition introduces phase and amplitude reflections in the signal. A kind of micro multi-path condition resulting in envelope distortion and signal phase errors when the reflections are recombined with the desired signal at the silicon. Managing this is a real headache. Think about a processor running say 6Ghz. The transitional bandwidth is actually 60-66 Ghz. The size of a disturbing feature becomes 300/60,000/32 (a thirty-second of a wavelength physical disturbance will produce unwanted effects such as SWR, and reflections along with radiation loss and so forth). This calculates to being approximately .0061 inches. Pretty tight system control. If you can stand some corner degredation, you can use the base frequency or 6Ghz, which gives you .06" but that is still pretty tight control, and you do lose some fidelity, which will affect product yield. Regards, Les H -- fedora-list mailing list fedora-list@xxxxxxxxxx To unsubscribe: https://www.redhat.com/mailman/listinfo/fedora-list
