From: Yanko Kaneti <yaneti@xxxxxxxxxxx>
Merge branch kernel-ark:os-build into ark-pci-realloc-auto
diff --git a/.mailmap b/.mailmap
index blahblah..blahblah 100644
--- a/.mailmap
+++ b/.mailmap
@@ -83,6 +83,13 @@ Anirudh Ghayal <quic_aghayal@xxxxxxxxxxx> <aghayal@xxxxxxxxxxxxxx>
Antoine Tenart <atenart@xxxxxxxxxx> <antoine.tenart@xxxxxxxxxxx>
Antoine Tenart <atenart@xxxxxxxxxx> <antoine.tenart@xxxxxxxxxxxxxxxxxx>
Antonio Ospite <ao2@xxxxxx> <ao2@xxxxxxxxxxxxxxxxxxxx>
+Antonio Quartulli <antonio@xxxxxxxxxxxxx> <antonio@xxxxxxxxxxxxxx>
+Antonio Quartulli <antonio@xxxxxxxxxxxxx> <antonio@xxxxxxxxxxxxx>
+Antonio Quartulli <antonio@xxxxxxxxxxxxx> <antonio.quartulli@xxxxxxxxxxxxx>
+Antonio Quartulli <antonio@xxxxxxxxxxxxx> <ordex@xxxxxxxxxxxxx>
+Antonio Quartulli <antonio@xxxxxxxxxxxxx> <ordex@xxxxxxxxxxxx>
+Antonio Quartulli <antonio@xxxxxxxxxxxxx> <antonio@xxxxxxxxxxx>
+Antonio Quartulli <antonio@xxxxxxxxxxxxx> <a@xxxxxxxxxxx>
Anup Patel <anup@xxxxxxxxxxxxxx> <anup.patel@xxxxxxx>
Archit Taneja <archit@xxxxxx>
Ard Biesheuvel <ardb@xxxxxxxxxx> <ard.biesheuvel@xxxxxxxxxx>
@@ -430,6 +437,8 @@ Marcin Nowakowski <marcin.nowakowski@xxxxxxxx> <marcin.nowakowski@xxxxxxxxxx>
Marc Zyngier <maz@xxxxxxxxxx> <marc.zyngier@xxxxxxx>
Marek Behún <kabel@xxxxxxxxxx> <marek.behun@xxxxxx>
Marek Behún <kabel@xxxxxxxxxx> Marek Behun <marek.behun@xxxxxx>
+Marek Lindner <marek.lindner@xxxxxxxxxxx> <lindner_marek@xxxxxxxx>
+Marek Lindner <marek.lindner@xxxxxxxxxxx> <mareklindner@xxxxxxxxxxxxx>
Mark Brown <broonie@xxxxxxxxxxxxx>
Mark Starovoytov <mstarovo@xxxxx> <mstarovoitov@xxxxxxxxxxx>
Markus Schneider-Pargmann <msp@xxxxxxxxxxxx> <mpa@xxxxxxxxxxxxxx>
@@ -532,6 +541,8 @@ Oleksij Rempel <linux@xxxxxxxxxxxxxxxx> <external.Oleksij.Rempel@xxxxxxxxxxxx>
Oleksij Rempel <linux@xxxxxxxxxxxxxxxx> <fixed-term.Oleksij.Rempel@xxxxxxxxxxxx>
Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx> <ore@xxxxxxxxxxxxxx>
+Oliver Hartkopp <socketcan@xxxxxxxxxxxx> <oliver.hartkopp@xxxxxxxxxxxxx>
+Oliver Hartkopp <socketcan@xxxxxxxxxxxx> <oliver@xxxxxxxxxxxx>
Oliver Upton <oliver.upton@xxxxxxxxx> <oupton@xxxxxxxxxx>
Ondřej Jirman <megi@xxxxxx> <megous@xxxxxxxxxx>
Oza Pawandeep <quic_poza@xxxxxxxxxxx> <poza@xxxxxxxxxxxxxx>
@@ -643,6 +654,11 @@ Simona Vetter <simona.vetter@xxxxxxxx> <daniel@xxxxxxxxxxxxxx>
Simon Horman <horms@xxxxxxxxxx> <simon.horman@xxxxxxxxxxxx>
Simon Horman <horms@xxxxxxxxxx> <simon.horman@xxxxxxxxxxxxx>
Simon Kelley <simon@xxxxxxxxxxxxxxxxx>
+Simon Wunderlich <sw@xxxxxxxxxxxxxxxxxx> <simon.wunderlich@xxxxxxxxxxxxx>
+Simon Wunderlich <sw@xxxxxxxxxxxxxxxxxx> <simon.wunderlich@xxxxxxxxxxxxxxxxxxxx>
+Simon Wunderlich <sw@xxxxxxxxxxxxxxxxxx> <simon.wunderlich@xxxxxxxxx>
+Simon Wunderlich <sw@xxxxxxxxxxxxxxxxxx> <simon@xxxxxxxxxxxxx>
+Simon Wunderlich <sw@xxxxxxxxxxxxxxxxxx> <siwu@xxxxxxxxxxxxxxxxxx>
Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx> <sricharan@xxxxxxxxxxxxxx>
Srinivas Ramana <quic_sramana@xxxxxxxxxxx> <sramana@xxxxxxxxxxxxxx>
Sriram R <quic_srirrama@xxxxxxxxxxx> <srirrama@xxxxxxxxxxxxxx>
@@ -663,6 +679,11 @@ Sudarshan Rajagopalan <quic_sudaraja@xxxxxxxxxxx> <sudaraja@xxxxxxxxxxxxxx>
Sudeep Holla <sudeep.holla@xxxxxxx> Sudeep KarkadaNagesha <sudeep.karkadanagesha@xxxxxxx>
Sumit Semwal <sumit.semwal@xxxxxx>
Surabhi Vishnoi <quic_svishnoi@xxxxxxxxxxx> <svishnoi@xxxxxxxxxxxxxx>
+Sven Eckelmann <sven@xxxxxxxxxxxxx> <seckelmann@xxxxxxxxx>
+Sven Eckelmann <sven@xxxxxxxxxxxxx> <sven.eckelmann@xxxxxx>
+Sven Eckelmann <sven@xxxxxxxxxxxxx> <sven.eckelmann@xxxxxxxxxxxxx>
+Sven Eckelmann <sven@xxxxxxxxxxxxx> <sven.eckelmann@xxxxxxxxxxxx>
+Sven Eckelmann <sven@xxxxxxxxxxxxx> <sven@xxxxxxxxxxxxx>
Takashi YOSHII <takashi.yoshii.zj@xxxxxxxxxxx>
Tamizh Chelvam Raja <quic_tamizhr@xxxxxxxxxxx> <tamizhr@xxxxxxxxxxxxxx>
Taniya Das <quic_tdas@xxxxxxxxxxx> <tdas@xxxxxxxxxxxxxx>
diff --git a/Documentation/Makefile b/Documentation/Makefile
index blahblah..blahblah 100644
--- a/Documentation/Makefile
+++ b/Documentation/Makefile
@@ -104,7 +104,7 @@ quiet_cmd_sphinx = SPHINX $@ --> file://$(abspath $(BUILDDIR)/$3/$4)
YNL_INDEX:=$(srctree)/Documentation/networking/netlink_spec/index.rst
YNL_RST_DIR:=$(srctree)/Documentation/networking/netlink_spec
YNL_YAML_DIR:=$(srctree)/Documentation/netlink/specs
-YNL_TOOL:=$(srctree)/tools/net/ynl/ynl-gen-rst.py
+YNL_TOOL:=$(srctree)/tools/net/ynl/pyynl/ynl_gen_rst.py
YNL_RST_FILES_TMP := $(patsubst %.yaml,%.rst,$(wildcard $(YNL_YAML_DIR)/*.yaml))
YNL_RST_FILES := $(patsubst $(YNL_YAML_DIR)%,$(YNL_RST_DIR)%, $(YNL_RST_FILES_TMP))
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index blahblah..blahblah 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -7172,6 +7172,14 @@
comma-separated list of trace events to enable. See
also Documentation/trace/events.rst
+ To enable modules, use :mod: keyword:
+
+ trace_event=:mod:<module>
+
+ The value before :mod: will only enable specific events
+ that are part of the module. See the above mentioned
+ document for more information.
+
trace_instance=[instance-info]
[FTRACE] Create a ring buffer instance early in boot up.
This will be listed in:
diff --git a/Documentation/core-api/packing.rst b/Documentation/core-api/packing.rst
index blahblah..blahblah 100644
--- a/Documentation/core-api/packing.rst
+++ b/Documentation/core-api/packing.rst
@@ -227,11 +227,119 @@ Intended use
Drivers that opt to use this API first need to identify which of the above 3
quirk combinations (for a total of 8) match what the hardware documentation
-describes. Then they should wrap the packing() function, creating a new
-xxx_packing() that calls it using the proper QUIRK_* one-hot bits set.
+describes.
+
+There are 3 supported usage patterns, detailed below.
+
+packing()
+^^^^^^^^^
+
+This API function is deprecated.
The packing() function returns an int-encoded error code, which protects the
programmer against incorrect API use. The errors are not expected to occur
-during runtime, therefore it is reasonable for xxx_packing() to return void
-and simply swallow those errors. Optionally it can dump stack or print the
-error description.
+during runtime, therefore it is reasonable to wrap packing() into a custom
+function which returns void and swallows those errors. Optionally it can
+dump stack or print the error description.
+
+.. code-block:: c
+
+ void my_packing(void *buf, u64 *val, int startbit, int endbit,
+ size_t len, enum packing_op op)
+ {
+ int err;
+
+ /* Adjust quirks accordingly */
+ err = packing(buf, val, startbit, endbit, len, op, QUIRK_LSW32_IS_FIRST);
+ if (likely(!err))
+ return;
+
+ if (err == -EINVAL) {
+ pr_err("Start bit (%d) expected to be larger than end (%d)\n",
+ startbit, endbit);
+ } else if (err == -ERANGE) {
+ if ((startbit - endbit + 1) > 64)
+ pr_err("Field %d-%d too large for 64 bits!\n",
+ startbit, endbit);
+ else
+ pr_err("Cannot store %llx inside bits %d-%d (would truncate)\n",
+ *val, startbit, endbit);
+ }
+ dump_stack();
+ }
+
+pack() and unpack()
+^^^^^^^^^^^^^^^^^^^
+
+These are const-correct variants of packing(), and eliminate the last "enum
+packing_op op" argument.
+
+Calling pack(...) is equivalent, and preferred, to calling packing(..., PACK).
+
+Calling unpack(...) is equivalent, and preferred, to calling packing(..., UNPACK).
+
+pack_fields() and unpack_fields()
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The library exposes optimized functions for the scenario where there are many
+fields represented in a buffer, and it encourages consumer drivers to avoid
+repetitive calls to pack() and unpack() for each field, but instead use
+pack_fields() and unpack_fields(), which reduces the code footprint.
+
+These APIs use field definitions in arrays of ``struct packed_field_u8`` or
+``struct packed_field_u16``, allowing consumer drivers to minimize the size
+of these arrays according to their custom requirements.
+
+The pack_fields() and unpack_fields() API functions are actually macros which
+automatically select the appropriate function at compile time, based on the
+type of the fields array passed in.
+
+An additional benefit over pack() and unpack() is that sanity checks on the
+field definitions are handled at compile time with ``BUILD_BUG_ON`` rather
+than only when the offending code is executed. These functions return void and
+wrapping them to handle unexpected errors is not necessary.
+
+It is recommended, but not required, that you wrap your packed buffer into a
+structured type with a fixed size. This generally makes it easier for the
+compiler to enforce that the correct size buffer is used.
+
+Here is an example of how to use the fields APIs:
+
+.. code-block:: c
+
+ /* Ordering inside the unpacked structure is flexible and can be different
+ * from the packed buffer. Here, it is optimized to reduce padding.
+ */
+ struct data {
+ u64 field3;
+ u32 field4;
+ u16 field1;
+ u8 field2;
+ };
+
+ #define SIZE 13
+
+ typdef struct __packed { u8 buf[SIZE]; } packed_buf_t;
+
+ static const struct packed_field_u8 fields[] = {
+ PACKED_FIELD(100, 90, struct data, field1),
+ PACKED_FIELD(90, 87, struct data, field2),
+ PACKED_FIELD(86, 30, struct data, field3),
+ PACKED_FIELD(29, 0, struct data, field4),
+ };
+
+ void unpack_your_data(const packed_buf_t *buf, struct data *unpacked)
+ {
+ BUILD_BUG_ON(sizeof(*buf) != SIZE;
+
+ unpack_fields(buf, sizeof(*buf), unpacked, fields,
+ QUIRK_LITTLE_ENDIAN);
+ }
+
+ void pack_your_data(const struct data *unpacked, packed_buf_t *buf)
+ {
+ BUILD_BUG_ON(sizeof(*buf) != SIZE;
+
+ pack_fields(buf, sizeof(*buf), unpacked, fields,
+ QUIRK_LITTLE_ENDIAN);
+ }
diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
+++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
@@ -43,6 +43,7 @@ properties:
- atmel,sama5d4-pmc
- microchip,sam9x60-pmc
- microchip,sam9x7-pmc
+ - microchip,sama7d65-pmc
- microchip,sama7g5-pmc
- const: syscon
@@ -90,6 +91,7 @@ allOf:
enum:
- microchip,sam9x60-pmc
- microchip,sam9x7-pmc
+ - microchip,sama7d65-pmc
- microchip,sama7g5-pmc
then:
properties:
diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
+++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
@@ -20,6 +20,7 @@ properties:
- items:
- enum:
- microchip,sam9x7-sckc
+ - microchip,sama7d65-sckc
- microchip,sama7g5-sckc
- const: microchip,sam9x60-sckc
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
new file mode 100644
index blahblah..blahblah 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm CMN PLL Clock Controller on IPQ SoC
+
+maintainers:
+ - Bjorn Andersson <andersson@xxxxxxxxxx>
+ - Luo Jie <quic_luoj@xxxxxxxxxxx>
+
+description:
+ The CMN (or common) PLL clock controller expects a reference
+ input clock. This reference clock is from the on-board Wi-Fi.
+ The CMN PLL supplies a number of fixed rate output clocks to
+ the devices providing networking functions and to GCC. These
+ networking hardware include PPE (packet process engine), PCS
+ and the externally connected switch or PHY devices. The CMN
+ PLL block also outputs fixed rate clocks to GCC. The PLL's
+ primary function is to enable fixed rate output clocks for
+ networking hardware functions used with the IPQ SoC.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq9574-cmn-pll
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: The reference clock. The supported clock rates include
+ 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
+ - description: The AHB clock
+ - description: The SYS clock
+ description:
+ The reference clock is the source clock of CMN PLL, which is from the
+ Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
+ clock registers.
+
+ clock-names:
+ items:
+ - const: ref
+ - const: ahb
+ - const: sys
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+
+ cmn_pll: clock-controller@9b000 {
+ compatible = "qcom,ipq9574-cmn-pll";
+ reg = <0x0009b000 0x800>;
+ clocks = <&cmn_pll_ref_clk>,
+ <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+ clock-names = "ref", "ahb", "sys";
+ #clock-cells = <1>;
+ assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
+ assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
@@ -78,6 +78,7 @@ allOf:
then:
properties:
clocks:
+ minItems: 8
items:
- description: Board PXO source
- description: PLL 3 clock
@@ -87,8 +88,10 @@ allOf:
- description: DSI phy instance 2 dsi clock
- description: DSI phy instance 2 byte clock
- description: HDMI phy PLL clock
+ - description: LVDS PLL clock
clock-names:
+ minItems: 8
items:
- const: pxo
- const: pll3
@@ -98,6 +101,7 @@ allOf:
- const: dsi2pll
- const: dsi2pllbyte
- const: hdmipll
+ - const: lvdspll
- if:
properties:
diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
new file mode 100644
index blahblah..blahblah 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on QCS615
+
+maintainers:
+ - Taniya Das <quic_tdas@xxxxxxxxxxx>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on QCS615.
+
+ See also: include/dt-bindings/clock/qcom,qcs615-gcc.h
+
+properties:
+ compatible:
+ const: qcom,qcs615-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board active XO source
+ - description: Sleep clock source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: bi_tcxo_ao
+ - const: sleep_clk
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,qcs615-gcc";
+ reg = <0x00100000 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
@@ -33,6 +33,8 @@ properties:
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
+ - qcom,rpmcc-msm8937
+ - qcom,rpmcc-msm8940
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
- qcom,rpmcc-msm8976
@@ -110,6 +112,8 @@ allOf:
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
+ - qcom,rpmcc-msm8937
+ - qcom,rpmcc-msm8940
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
- qcom,rpmcc-msm8976
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
@@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
+ - qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk
- qcom,sar2130p-rpmh-clk
@@ -37,6 +38,7 @@ properties:
- qcom,sm8450-rpmh-clk
- qcom,sm8550-rpmh-clk
- qcom,sm8650-rpmh-clk
+ - qcom,sm8750-rpmh-clk
- qcom,x1e80100-rpmh-clk
clocks:
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
@@ -18,12 +18,6 @@ description: |
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
properties:
- clocks: true
-
- clock-names: true
-
- reg: true
-
compatible:
enum:
- qcom,sc7280-lpassaoncc
@@ -31,12 +25,24 @@ properties:
- qcom,sc7280-lpasscorecc
- qcom,sc7280-lpasshm
- power-domains:
- maxItems: 1
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
'#clock-cells':
const: 1
+ power-domains:
+ maxItems: 1
+
'#power-domain-cells':
const: 1
@@ -57,8 +63,6 @@ required:
- '#clock-cells'
- '#power-domain-cells'
-additionalProperties: false
-
allOf:
- if:
properties:
@@ -125,6 +129,9 @@ allOf:
reg:
maxItems: 1
+
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml
@@ -20,7 +20,11 @@ allOf:
properties:
compatible:
- const: qcom,sdm845-camcc
+ oneOf:
+ - items:
+ - const: qcom,sdm670-camcc
+ - const: qcom,sdm845-camcc
+ - const: qcom,sdm845-camcc
clocks:
items:
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
new file mode 100644
index blahblah..blahblah 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controller on SM6115
+
+maintainers:
+ - Konrad Dybcio <konradybcio@xxxxxxxxxx>
+ - Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
+
+description: |
+ Qualcomm LPASS core and audio clock controllers provide audio-related resets
+ on SM6115 and its derivatives.
+
+ See also::
+ include/dt-bindings/clock/qcom,sm6115-lpasscc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm6115-lpassaudiocc
+ - qcom,sm6115-lpasscc
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ lpass_audiocc: clock-controller@a6a9000 {
+ compatible = "qcom,sm6115-lpassaudiocc";
+ reg = <0x0a6a9000 0x1000>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
@@ -19,7 +19,6 @@ description: |
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sm8650-camcc.h
- include/dt-bindings/clock/qcom,x1e80100-camcc.h
properties:
compatible:
@@ -29,7 +28,6 @@ properties:
- qcom,sm8475-camcc
- qcom,sm8550-camcc
- qcom,sm8650-camcc
- - qcom,x1e80100-camcc
clocks:
items:
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
@@ -32,6 +32,7 @@ properties:
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
- qcom,x1e80100-gpucc
+ - qcom,x1p42100-gpucc
clocks:
items:
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
@@ -12,11 +12,12 @@ maintainers:
description: |
Qualcomm display clock control module provides the clocks, resets and power
- domains on SM8550.
+ domains on SM8550, SM8650, SM8750 and few other platforms.
See also:
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
+ - include/dt-bindings/clock/qcom,sm8750-dispcc.h
- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
properties:
@@ -25,6 +26,7 @@ properties:
- qcom,sar2130p-dispcc
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc
+ - qcom,sm8750-dispcc
- qcom,x1e80100-dispcc
clocks:
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
index blahblah..blahblah 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
@@ -16,6 +16,7 @@ description: |
See also:
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
+ - include/dt-bindings/clock/qcom,sm8750-tcsr.h
properties:
compatible:
@@ -24,6 +25,7 @@ properties:
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
+ - qcom,sm8750-tcsr
- qcom,x1e80100-tcsr
- const: syscon
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
new file mode 100644
index blahblah..blahblah 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8750-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on SM8750
+
+maintainers:
+ - Taniya Das <quic_tdas@xxxxxxxxxxx>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on SM8750
+
+ See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
+
+properties:
+ compatible:
+ const: qcom,sm8750-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board Always On XO source
+ - description: Sleep clock source
+ - description: PCIE 0 Pipe clock source
+ - description: UFS Phy Rx symbol 0 clock source
+ - description: UFS Phy Rx symbol 1 clock source
+ - description: UFS Phy Tx symbol 0 clock source
+ - description: USB3 Phy wrapper pipe clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,sm8750-gcc";
+ reg = <0x00100000 0x001f4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie0_phy>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
+ <&usb_1_qmpphy>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml
new file mode 100644
index blahblah..blahblah 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,x1e80100-camcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller on x1e80100
+
+maintainers:
+ - Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
+
+description: |
+ Qualcomm camera clock control module provides the clocks, resets and power
+ domains on x1e80100.
+
+ See also:
+ include/dt-bindings/clock/qcom,x1e80100-camcc.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,x1e80100-camcc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Camera AHB clock from GCC
+ - description: Board XO source
+ - description: Board active XO source
+ - description: Sleep clock source
+
+ power-domains:
+ items:
+ - description: A phandle to the MXC power-domain
+ - description: A phandle to the MMCX power-domain
+
+ required-opps:
+ maxItems: 1
+ description:
+ A phandle to an OPP node describing MMCX performance points.
+
+required:
+ - compatible
+ - clocks
+ - power-domains
+ - required-opps
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@ade0000 {
+ compatible = "qcom,x1e80100-camcc";
+ reg = <0xade0000 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
--
https://gitlab.com/cki-project/kernel-ark/-/merge_requests/3622
--
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