Hi,
I have the following code for an inverter:
============================
--inverter (NOT) gate
entity invg is port
(
a : in bit;
x : out bit;
vdd : in bit;
vss : in bit
);
end invg;
architecture vbe of invg is begin
x <= not (a);
end vbe;
============================
I saved this in invg.vbe Next I ran the following commands:
boom -l 3 -d invg
boog invg_o invg -x 1 -m 2
This resulted in the file invg.vst which contains the following:
============================
entity invg is
port (
a : in bit;
x : out bit;
vdd : in bit;
vss : in bit
);
end invg;
architecture structural of invg is
Component inv_x2
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
x_ins : inv_x2
port map (
i => a,
nq => x,
vdd => vdd,
vss => vss
);
end structural;
============================
I now created a pattern to drive the input. However I see a ?u in the
output. I ran the following command
asimut invg invg invg_out
I do not see this problem when I run behavioral simulations. The
output patterns file is as below. The input file contains ?* instead
of the ?u
============================
-- description generated by Pat driver
-- date : Sun May 20 14:50:49 2012
-- revision : v109
-- sequence : invg
-- input / output list :
in vdd B;
in vss B;
in a B;
out x B;
begin
-- Pattern description :
-- vva x
-- ds
-- ds
: 100?u;
: 101?u;
end;
============================
Is there something I'm doing wrong that is causing the output to show
as undefined?
The code is from this e-book which I am using to learn about the
alliance package:
http://www.cc.toin.ac.jp/sc/palacios/openbook/vlsie.pdf (1.8MB)
Thanks,
Ashwith J. Rego
-----------------
My Webpage: http://ashwith.wordpress.com/
Find me on LinkedIn at: http://www.linkedin.com/in/ashwith
Follow Me on Twitter at: http://twitter.com/Louisda16th
_______________________________________________
electronic-lab mailing list
electronic-lab@xxxxxxxxxxxxxxxxxxxxxxx
https://admin.fedoraproject.org/mailman/listinfo/electronic-lab
