Hi, I have two questions. 1. Are there any alternatives to Xilinx's System generator? Possibly something that converts octave or scilab (preferably xcos) code to VHDL or Verilog. 2. What sort of support is available for SystemVerilog in FEL? Thanks Ashwith J. Rego ----------------- My Webpage: http://ashwith.wordpress.com/ Find me on LinkedIn at: http://www.linkedin.com/in/ashwith Follow Me on Twitter at: http://twitter.com/Louisda16th _______________________________________________ electronic-lab mailing list electronic-lab@xxxxxxxxxxxxxxxxxxxxxxx https://admin.fedoraproject.org/mailman/listinfo/electronic-lab
