Hello, Thank you for this robust platform for digital design. I'm a digital designer. I was using iverilog and gtkwave on ubuntu. However last year, I had a lot of issues when doing maths with verilog. Then I tried Fedora to see if if suffers these issues, but haven't encountered any. I was impressed and sticked with Fedora ever since. With the recent gplcver and vrq, it makes verilog design exciting. In the meantime, I'm learning vhdl on my own and am unable to get the name of the current state of the state machine on gtkwave. Is there a solution for that so that I don't have to declare a special non-synthesized std_logic_vector. Nigel _______________________________________________ Fedora-electronic-lab-list mailing list Fedora-electronic-lab-list@xxxxxxxxxx https://www.redhat.com/mailman/listinfo/fedora-electronic-lab-list
