#58: package covered
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Reporter: chitlesh | Owner: chitlesh
Type: task | Status: new
Priority: major | Milestone: Fedora 13
Component: VHDL/Verilog | Version: devel
Keywords: |
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http://sourceforge.net/projects/covered/
Covered is a Verilog code coverage utility using VCD/LXT dumpfiles (or VPI
simulation interface) and the design to generate line, toggle, memory,
combinational logic, FSM state/arc and assertion coverage report metrics
viewable via GUI or ASCII format.
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Ticket URL: <https://fedorahosted.org/fedora-electronic-lab/ticket/58>
Fedora Electronic Lab <https://fedorahosted.org/fedora-electronic-lab>
Design, Simulate and Program electronics.
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