On Sun, Jun 7, 2009 at 11:27 AM, Chitlesh GOORAH<chitlesh@xxxxxxxxxxxxxxxxx> wrote: > We already have a design flow that enables users to design their > chips. Hence as a case example users can design their 8051/8085 chips > with alliance/magic design flow and use the 8085/8051 simulators to > simulate their code they will program on the chips. This is how I see > those simulators very handy. I hope during that meeting we can talk > about this and what we can do to improve design experience ? Very interesting perspective. I would like to attend this meeting to see what improvement can be done to gnusim8085 being one of the upstream developers. CC'ing gnusim8085-devel list too. > What do you think ? Tell me when does it suit you. My schedule for this week is very dynamic but neverthless do let me know the times too. I will try my best to be there. wkr, A _______________________________________________ Fedora-electronic-lab-list mailing list Fedora-electronic-lab-list@xxxxxxxxxx https://www.redhat.com/mailman/listinfo/fedora-electronic-lab-list
