Of course there is no troubles with Veriog/VHDL etc. code and revision
control and tracking must be used there. No doubt about that. Do you
think though it should be any different from the "usual" open source flow?
Regards
Svilen
Chitlesh GOORAH wrote:
On Sun, Mar 1, 2009 at 2:35 PM, Svilen wrote:
Correct me if I'm wrong, but neither of FEL tools
offer a tool suitable to be used as an external diff for the binary formats
they are dealing with. By the way - the situation is very similar with
commercial tools. In result - all binary data used by FEL tools can't be
stored incrementally in the databases of any of the revision control
systems
Hello Svilen,
You are partially right here. However for digital design, a revision
control for vhdl and verilog is useful, especially if there are many
designers. With the perl modules for vhdl and verilog being included
for F11, digital designers can expand their home made design flow by
using those modules in their own perl scripts. Some perl modules could
even be used for co-simulation or co-verification purposes as well.
Example, memory based verilog designs
powercraft.nl already use svn for geda and pcb based projects :
http://www.powercraft.nl/websvn/listing.php?repname=OpenARM+Single-board+Computer&path=%2Ftrunk%2Fworking%2F#_trunk_working_
This is my reason behind this trac/git/svn discussion. Unfortunately
this does not apply to each FEL apps.
regards,
chitlesh
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